Researchers from ETH Zurich have discovered a novel Spectre V2 variant that impacts AMD Zen 1 through Zen 4 CPUs via the CPU’s return address predictor. Researchers have called this attack 'Inception'. AMD calls this Speculative Return Stack Overflow and has titled this AMD-SN-7005 Return Address Predictor Security Notice.
A given hardware thread may poison the branch predictors in the CPU core and use that to trick the CPU to access information in another context. Oxide gimlet servers are impacted by this vulnerability. Oxide is reviewing the guidance and expected performance impact from AMD and is awaiting publication of the research paper which should occur on Aug 9, 2023 so we can further analyze this vulnerability and provide additional guidance.
| Revision | Date (YYYYMMDD) | Changes |
|---|---|---|
1.0 | 20230808 | Initial Release |
Impacted Products
This impacts all Gimlet Compute Sleds.
Impact
An attacker in a virtual machine may be able to read privileged information through a cache-timing side channel attack from the hypervisor or from the guest operating sytems’s kernel that is executing on the same thread or core as the attacker.
Action Required
There is no immediate action required for Oxide systems. We will provide additional updates as we better understand this situation. Any mitigations will likely be part of the next software update. Oxide is evaluating the isolation of indirect branch predictors as well as reviewing what is required to ensure that guest virtual machines will be able to properly understand this based on information that will be released by the Linux kernel project and Microsoft.
The required microcode revision for Oxide’s Gimlet systems (0x0a0011d1) was already a part of Oxide Software Release 1.0.1.
Mitigations
Reducing the number of untrusted workloads may reduce the chance of this attack being executed. The primary means of exploitation in Oxide products is through hardware virtual machine guests that are created through the API.
Technical Background
As part of optimizing common function calls and branches in the
processor, the hardware maintains what it calls a Return Address Stack.
When a processor executes the call instruction, it pushes the return
address on to the operating system stack and makes a note of it in
inside the processor itself. The processor-internal structure is called
the Return Address Stack (RAS). This is used because most
subroutines/function calls will return to whence they came allowing the
CPU to optimize this case. The RAS contains the full address of the
target. Only addresses that are valid in the current address space
(based on the %cr3 register) can enter the RAS.
In addition to the RAS, the CPU employs what is known as a branch target buffer (BTB). The CPU caches the location that a branch instruction will likely go to as part of its speculative execution engine. Put differently, when the CPU is scanning ahead and sees a branch instruction, it will guess on what path the program will jump to and speculatively execute assuming that is correct. It will then later come back and determine whether or not that is actually correct.
The AMD BTB design found in Zen family CPUs does not include the full instruction pointer inside of it, it instead includes a subset of the address bits. This means that entries in the BTB may alias several different virtual addresses in the CPU. Due to the aliasing, it is possible to cause confusion inside the RAS and cause the CPU to mispredict a return instruction.
A mispredicted instruction is then, when combined with the proper gadget, used to cause the CPU to create a side-effect in the cache that may be observable. The RAS exists on a per-thread basis. That is, each hardware thread has an independent return address stack. However, depending on the CPU configuration the BTB may be shared between hardware threads in the core. This leads to some theoretical difficulties in performing the attack. We expect additional information about this to be clearer when the research paper is made available.
AMD is releasing a microcode update for AMD Zen 3 and Zen 4 systems that will change the behavior of the Indirect Branch Prediction Barrier (IBPB) MSR which is used to flush out older indirect branch predictions. Microcode updates are not required for AMD Zen 1 and 2 systems. Existing CPU microcode on Zen 1 and 2 systems performs all necessary flushes on an IBPB. Proper use of IBPB when combined with the Single-thread indirect branch predictors, can significantly mitigate this attack according to AMD.